(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for forming one or more levels of damascene structures whereby (via and contact) holes are formed at the same time that (interconnect) wire lines are formed.
(2) Description of the Prior Art
In the formation of semiconductor integrated circuits, it is common practice to form interconnect metal line structures on a number of different levels within the structure and interconnecting the various levels of wiring with contact or via openings. The first or lowest level of interconnect wires is typically formed as a first step in the process after which a second or overlying level of interconnect wires is deposited over the first level. The first level of interconnect wires is typically in contact with active regions in a semiconductor substrate but is not limited to such contact. The first level of interconnect can for instance also be in contact with a conductor that leads to other devices that form part of a larger, multi-chip structure. The two levels of metal wires are connected by openings between the two layers that are filled with metal where the openings between the two layers line up with and match contact points in one or both of the levels of metal lines.
Previously used techniques to form multi-levels of wiring apply the technique of first forming the interconnect level metal in a first plane followed by forming the overlying level of interconnect wire in a second plane. This structure typically starts with the surface of a semiconductor substrate into which active devices have been created. These active devices can include bipolar transistors, MOSFET devices, doped regions that interconnect with other regions of the device while provisions may also have been provided to make interconnects with I//O terminals in the periphery of the device. The surface into which the pattern of interconnect lines of the first plane is formed may also be an insulation layer deposited over the surface of the substrate or a layer of oxide may first have been formed on the surface of the substrate. After the layer, into which the pattern of interconnecting wires has to be created, has been defined, the interconnecting pattern itself needs to be defined. This is done using conventional photolithographic techniques whereby the openings are made (in the layer) above the points that need to be contacted in the substrate. The openings, once created, may by lined with layers of material to enhance metal adhesion (to the sidewalls of the opening), the glue or seed layer, or to prevent diffusion of materials into and from the damascene structure in subsequent processing steps, the barrier layer. For the barrier layer, a variety of materials can be used such as Ti/TiN:W (titanium/titanium nitride:tungsten), titanium-tungsten/titanium or titanium-tungsten nitride/titanium or titanium nitride or titamium nitride/titanium, tungsten, tantalum or its compounds, niobium, molybdenum. The final phase in creating the first level of interconnect lines is to fill the created openings with metal, typically aluminum, tungsten or copper, dependent on the particular application and requirements and restrictions imposed by such parameters as line width, aspect ratio of the opening, required planarity of the surface of the deposited metal and others.
This process of line formation in overlying layers of metal can be repeated in essentially the same manner as just highlighted for the first layer of interconnecting wires. This process of forming sequential layers of interconnecting levels of wire is in many instances prone to problems and limitations. The use of copper has in recent times found more application in the use of metal wires due to its low resistivity, high electromigration resistance and stress voiding resistance. Copper however exhibits the disadvantage of high diffusivity in common insulating materials such as silicon oxide and oxygen-containing polymers. This leads to, for instance, the diffusion of copper into polyimide during high temperature processing of the polyimide resulting in severe corrosion of the copper and the polyimide due to the copper combining with oxygen in the polyimide. The corrosion may result in loss of adhesion, delamination, voids, and ultimately a catastrophic failure of the component. A copper diffusion barrier is therefore often required. Furthermore, due to the fact that copper is very difficult to process by RIE, the CMP method may need to be used where copper is used as a wiring material. To polish copper at a high rate without scratching in accordance with the buried wiring formation, the copper etch rate must be raised by increasing the amount of the component responsible for copper etching contained in the polishing slurry. If the component is used in an increased amount, the etching will occur isotropically. Consequently, buried copper is etched away, causing dishing in the wiring. It is, when forming interconnect lines using copper, desirable to use methods that do not depend on patterning the copper lines using a chemical etching process since etching of copper is very difficult and is a process that is only recently being further investigated. The use of copper as a metal for interconnect wiring is further hindered by copper's susceptibility to oxidation. Conventional photoresist processing cannot be used when the copper is to be patterned into various wire shapes because the photoresist needs to be removed at the end of the process by heating it in a highly oxidized environment, such as an oxygen plasma, thereby converting it to an easily removed ash.
Further problems of forming multi-layers of interconnect lines using the methods indicated above result from the continuing trend of micro-miniaturization in the semiconductor industry. This trend leads to ever decreasing device features and with that, decreasing line width. To deposit metals into these narrow lines is a difficult process where problems of proper line profiling, voids in the deposited metal and the trapping of impurities lead to serious restraints on the manufacturing process. Where a larger number of interconnecting lines are required, the number of processing steps required to create these lines may also become excessive thereby increasing processing steps and creating potentially serious yield detractors. It is therefore desirable to use processes that combine some of the above indicated steps and create for instance via openings at the same time as or in combination with the creation of the interconnect wire pattern.
Two widely used approaches in creating metal interconnects is the use of the damascene and the dual damascene structures. The application of the Damascene process continues to gain wider acceptance, most notably in the process of copper metalization due to the difficulty of copper dry etch where the Damascene plug penetrates deep in very small, sub-half micron, Ultra Large Scale Integrated devices. Recent applications have successfully used copper as a conducting metal line, most notably in the construct of CMOS 6-layer copper metal devices.
In the formation of a damascene structure, a metal plug is first formed in a surface; this surface in most instances is the surface of a semiconductor substrate. A layer of Intra Level Dielectric (ILD) is deposited (using for instance Plasma Enhanced CVD technology with SiO.sub.2 as a dielectric) over the surface into which trenches for metal lines are formed (using for instance Reactive Ion Etching technology).
The trenches overlay the metal plug and are filled with metal (using for instance either the CVD or a metal flow process). Planarization of this metal to the top surface of the layer of ILD completes the damascene structure. Some early damascene structures have been achieved using Reactive Ion Etching (RIE) for the process of planarization but Chemical Mechanical Planarization (CMP) is used exclusively today.
An extension of the damascene process is the dual damascene process whereby an insulating or dielectric material, such as silicon oxide, is patterned with several thousand openings for the conductive lines and vias, which are filled at the same time with metal. Damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal to form the conductive lines. Dual damascene is a multi-level interconnection process in which, in-addition to forming the grooves of single damascene, conductive via openings also are formed. One of the dual damascene approaches uses a dielectric layer that is formed by three consecutive depositions whereby the central layer functions as an etch stop layer. This etch stop layer can be SiN, the top and bottom dielectric layer of this three layer configuration can be SiO.sub.2. This triple layer dielectric allows first forming the vias by resist patterning the vias and etching through the two layers of dielectric and the central stop layer. The conductive pattern can then be formed in the top layer of dielectric whereby the central layer of SiN forms the stop layer for the etch of the conducting pattern. Another approach, still using the three-layer dielectric formed on the substrate surface, is to first form the pattern for the conducting lines in the top layer of the dielectric whereby the SiN layer again serves as etch stop. The vias can then be formed by aligning the via pattern with the pattern of the conducting lines and patterning and etching the vias through the etch stop layer of SiN and the first layer of dielectric. Yet another approach is to deposit the three layer dielectric in two steps, first depositing the first layer of SiO.sub.2 and the etch stop layer of SiN. At this point the via pattern can be exposed and etched. The top layer of SiO.sub.2 dielectric is then deposited; the conducting lines are now patterned and etched. The SiN layer will stop the etching except where the via openings have already been etched.
Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps.
Aluminum damascene structures can be fabricated using a planarized aluminum deposition process to fill sub-half micron geometry etched in oxide after which CMP is performed to remove the excess aluminum over the field region. Both single damascene, where vias only are created, and dual damascene, where vias are created and conductors are created above the vias, can be fabricated in this manner. For the dual damascene, special etch procedures can be used to form both the vias and the conductor patterns in the dielectric layer before the deposition of aluminum and the aluminum CMP. A thin etch stop layer was used for this purpose between two layers of dielectric SiO.sub.2.
One of the approaches that can be used in creating a dual damascene structure is further highlighted here to show the importance that multiple stop layers interspersed with multiple layers of passivation or dielectric can have in this process. A first etch stop layer is first deposited over the surface of a substrate. A first passivation layer of, for instance SiO2, is deposited over the first etch stop layer, followed by a thin layer of SiN as second etch stop, followed by the via resist patterning and etching of the second stop layer. This is followed by depositing the top layer of dielectric, a third etch stop layer may be deposited over the surface of the second dielectric. The conductor patterning can be formed in the third etch stop layer. In etching the conductor pattern in the top dielectric layer, the etching process will be stopped by the second stop layer except where the via holes are already opened in the second stop layer thereby completing the simultaneous via hole etching in the passivation layer.
The invention addresses the process of creating a dual damascene structure with the creation of holes and interconnect wiring patterns. Etch stop layers are used during this process.
U.S. Pat. No. 5,801,094 (Yew et al.) teaches a dual damascene process that forms (dual damascene) holes (vias and contact) and wiring lines (interconnect lines) simultaneously, see FIGS. 15 to 21, claim 1. The invention uses etch stop layers 54 between the dielectric layers 52 and 58.
U.S. Pat. No. 4,789,648 (Chow) shows a method for producing co-planar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias.
U.S. Pat. No. 5,229,257 (Cronin et al.) teaches a multi-level conductor using a polyimide insulator.
U.S. Pat.No. 5,598,027 (Matsuura) shows a damascene interconnect process with etch stops.